 
Summary: AMERICAN UNIVERSITY OF BEIRUT
FACULTY OF ENGINEERING AND ARCHITECTURE
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
EECE691C Digital Signal Processing Laboratory Week 9
FFT Implementation lab
The experiment objective is to implement the radix 2 FFT algorithm explained last
week. Figure 1 shows he different topologies to implement the FFT; you can either use
Decimation in time (DIT) or decimation in frequency (DIF). Depending on the topology you
may have the input or the output bit reversed. In addition some topologies multiply the input
from the previous stage by the twiddle factor before the butterfly implementation while others
multiply by the twiddle factor after butterfly implementation.
In the lab, the design code will be based on the topology of Figure 1 (a) where the
building block is the butterfly shown below in details:
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(a) Butterfly  Simplified (b) Butterfly  Detailed
The equation relating the output of the butterfly to the input is:
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