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Design of a Single Event Upset (SEU) Mitigation Technique for Programmable Devices
 

Summary: Design of a Single Event Upset (SEU) Mitigation Technique for
Programmable Devices
S. Baloch1,2
, T. Arslan1,2
, A. Stoica2,3
1: Institute for System Level Integration, Alba Centre, Alba Campus, Livingston, EH54 7EG, UK
2: School of Electronics & Engg, University of Edinburgh, Kings Buildings, Edinburgh,EH9 3JL, UK
3: Jet Propulsion Laboratory, NASA, 4800 Oak Grove Drive Pasadena, CA 91109, USA
Abstract
This paper presents a unique SEU (single Event
Upset) mitigation technique based upon Temporal
Data Sampling for synchronous circuits and
configuration bit storage for programmable devices.
The design technique addresses both conventional
static SEUs and SETs (Single Event Transients)
induced errors that can result in data loss for
reconfigurable architectures. The proposed scheme not
only eliminates all SEUs and SETs and but also all
double event upsets as well. This approach permits
FPGAs and other microcircuits with deep submicron

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering