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Summary: Fault Tolerant Clockless Wave Pipeline Design
T. Feng, B.Jin, *J.Wang and N.Park
Department of Computer Science
Department of Electrical and Computer Engineering
Oklahoma State University, Stillwater, OK 74078-1053
npark@cs.okstate.edu
Y.B. Kim and F. Lombardi
Department of Electrical and Computer Engineering
Northeastern University, Boston, MA 02115
lombardi@ece.neu.edu
Abstract
This paper presents a fault tolerant design technique for the clockless wave pipeline. The spe-
cific architectural model investigated in this paper is the two-phase clockless asynchronous wave
pipeline [10] which is ideally supposed to yield the theoretical maximum of performance. Re-
quest signal is the most critical component for the clockless-induced control of the wave pipelined
processing of data. In practice, the request signal is very sensitive and vulnerable to electronic
crosstalk noise, and this problem has become exteremely stringent for the ultra-high density in-
tegrated circuits today. Electronic noise may devastate the operational confidence level of the
clockless wave pipeline. In this context, this paper characterizes the yield and reliability properties
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