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Fractional-N Direct Digital Frequency Synthesis with a 1-Bit Output Jeremy Rode, Ashok Swaminathan, Ian Galton, and Peter M. Asbeck
 

Summary: 415
Fractional-N Direct Digital Frequency Synthesis with a 1-Bit Output
Jeremy Rode, Ashok Swaminathan, Ian Galton, and Peter M. Asbeck
University of California, San Diego, La Jolla, CA, 92093, USA
Abstract - A novel digital frequency synthesis (DDS)
architecture with a 1-bit output is proposed, simulated, and
demonstrated. A new noise shaping quantization algorithm is
also evaluated and used within the proposed DDS system. Large
tuning ranges and rapid (open loop) response characteristics are
achieved with only a static reference frequency input, without the
use of analog components, allowing easy integration in digital
CMOS processes. Across a tuning range of 10% fref, a noise floor
of -80 dBc/Hz and spurious tones lower than -50 dBc are possible
with this system.
Index Terms Frequency synthesizers, Sigma-delta
modulation, Quantization, CMOS digital integrated circuits.
I. INTRODUCTION
Frequency synthesis is a pervasive requirement in wireless
communication systems. Traditional frequency synthesis
techniques include phased locked loops (PLL) and direct

  

Source: Asbeck, Peter M. - Department of Electrical and Computer Engineering, University of California at San Diego
Galton, Ian - Department of Electrical and Computer Engineering, University of California at San Diego

 

Collections: Engineering