Home

About

Advanced Search

Browse by Discipline

Scientific Societies

E-print Alerts

Add E-prints

E-print Network
FAQHELPSITE MAPCONTACT US


  Advanced Search  

 
Predictive Line Buffer: A fast, Energy Efficient Cache Architecture
 

Summary: Predictive Line Buffer: A fast, Energy Efficient
Cache Architecture
Kashif Ali MoKhtar Aboelaze SupraKash Datta
Department of Computer Science and Engineering
York University
Toronto ON CANADA
Abstract
Two of the most important factors in the design of any processor
are speed and energy consumption. In this paper, we propose a new
cache architecture that results in a faster memory access and lower
energy consumption. Our proposed architecture does not require any
changes to the processor architecture, it only assume the existence of a
BTB. Using Mediabench, a benchmark used for embedded applications,
Simplescalar simulator, and CACTI power simulator,we show that our
proposed architecture consumes less energy, and have better memory
access time, than many existing cache architectures.
1 Introduction
The processor speed is advancing at a much higher rate than the memory
access speed. The cache memory is generally considered to be the only
solution to bridge the gap between the processor speed and the memory

  

Source: Aboelaze, Mokhtar - Department of Computer Science, York University (Toronto)

 

Collections: Computer Technologies and Information Sciences