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In Proceedings of the 4th International Symposium on High Performance Computing (ISHPC), May 2002, (c) Springer-Verlag. High Performance and Energy Efficient Serial Prefetch Architecture
 

Summary: In Proceedings of the 4th International Symposium on High Performance Computing (ISHPC), May 2002, (c) Springer-Verlag.
High Performance and Energy Efficient Serial Prefetch Architecture
Glenn Reinman Brad Caldery
Todd Austinz
Computer Science Department, University of California, Los Angeles
y
Department of Computer Science and Engineering, University of California, San Diego
z
Electrical Engineering and Computer Science Department, University of Michigan
Abstract
Energy efficient architecture research has flourished recently, in an attempt to address packaging
and cooling concerns of current microprocessor designs, as well as battery life for mobile computers.
Moreover, architects have become increasingly concerned with the complexity of their designs in the
face of scalability, verification, and manufacturing concerns.
In this paper, we propose and evaluate a high performance, energy and complexity efficient front-end
prefetch architecture. This design, called Serial Prefetching, combines a high fetch bandwidth branch
prediction and efficient instruction prefetching architecture with a low-energy instruction cache. Serial
Prefetching explores the benefit of decoupling the tag component of the cache from the data component.
Cache blocks are first verified by the tag component of the cache, and then the accesses are put into
a queue to be consumed by the data component of the instruction cache. Energy is saved by only

  

Source: Austin, Todd M. - Department of Electrical Engineering and Computer Science, University of Michigan
Calder, Bradley - Department of Computer Science and Engineering, University of California at San Diego
Sair, Suleyman - Department of Electrical and Computer Engineering, North Carolina State University

 

Collections: Computer Technologies and Information Sciences; Engineering