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Summary: Address Compression and Heterogeneous Interconnects for Energy-Efficient
High-Performance in Tiled CMPs
Antonio Flores, Manuel E. Acacio and Juan L. Arag´on
Departamento de Ingenier´ia y Tecnolog´ia de Computadores
University of Murcia, 30100 Murcia, Spain
{aflores, meacacio, jlaragon}@ditec.um.es
Abstract
Previous studies have shown that the interconnection
network of a Chip-Multiprocessor (CMP) has significant
impact on both overall performance and energy consump-
tion. Moreover, wires used in such interconnect can
be designed with varying latency, bandwidth and power
characteristics. In this work, we present a proposal for
performance- and energy-efficient message management in
tiled CMPs that combines both address compression with a
heterogeneous interconnect. Our proposal consists of ap-
plying an address compression scheme that dynamically
compresses the addresses within coherence messages al-
lowing for a significant area slack. The arising area can be
exploited for wire latency improvement by using a hetero-
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