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Technical Report UCB//CSD-05-1412, September 2005 RAMP: Research Accelerator for Multiple Processors -
 

Summary: Technical Report UCB//CSD-05-1412, September 2005
RAMP: Research Accelerator for Multiple Processors -
A Community Vision for a Shared Experimental Parallel HW/SW Platform
Arvind (MIT), Krste Asanovi´c (MIT), Derek Chiou (UT Austin), James C. Hoe (CMU),
Christoforos Kozyrakis (Stanford), Shih-Lien Lu (Intel), Mark Oskin (U Washington),
David Patterson (UC Berkeley), Jan Rabaey (UC Berkeley), and John Wawrzynek (UC Berkeley)
Project Summary
Desktop processor architectures have crossed a critical threshold. Manufactures have given up attempting to extract
ever more performance from a single core and instead have turned to multi-core designs. While straightforward
approaches to the architecture of multi-core processors are sufficient for small designs (2­4 cores), little is really
known how to build, program, or manage systems of 64 to 1024 processors. Unfortunately, the computer architecture
community lacks the basic infrastructure tools required to carry out this research. While simulation has been adequate
for single-processor research, significant use of simplified modeling and statistical sampling is required to work in the
2­16 processing core space. Invention is required for architecture research at the level of 64­1024 cores.
Fortunately, Moore's law has not only enabled these dense multi-core chips, it has also enabled extremely dense
FPGAs. Today, for a few hundred dollars, undergraduates can work with an FPGA prototype board with almost as
many gates as a Pentium. Given the right support, the research community can capitalize on this opportunity too.
Today, one to two dozen cores can be programmed into a single FPGA. With multiple FPGAs on a board and multiple
boards in a system, large complex architectures can be explored. To make this happen, however, requires a significant
amount of infrastructure in hardware, software, and what we call "gateware", the register-transfer level models that

  

Source: Asanovic, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)
Kozyrakis, Christos - Departments of Electrical Engineering & Computer Science, Stanford University
Wawrzynek, John - Department of Electrical Engineering and Computer Sciences, University of California at Berkeley

 

Collections: Computer Technologies and Information Sciences