Summary: A Framework for Scheduler Synthesis
K. Altisen, G. G¨oßler, A. Pnueli, J. Sifakis, S. Tripakis, and S. Yovine
Verimag, Centre '
Equation, 2 Ave. de Vignate, 38610 Gi`eres, France
faltisen,goessler,pnueli,sifakis,tripakis,yovineg@imag.fr
Abstract
In this paper we present a framework integrating
specification and scheduler generation for real­time sys­
tems. In a first step, the system, which can in­
clude arbitrarily designed tasks (cyclic or sporadic, with
or without precedence constraints, any number of re­
sources and CPUs) is specified as a timed Petri­net. In
a second step, our tool generates the most general non­
preemptive online scheduler for the specification, using
a controller synthesis technique.
1 Introduction
A complex real­time system is typically composed
of several tasks that interact. The execution of each
task is subject to different kinds of constraints, some of
which are proper to the task such as completion times,

Source: Altisen, Karine - Laboratoire VERIMAG, Centre National de la Recherche Scientifique (CNRS)

Collections: Computer Technologies and Information Sciences