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1918 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--I: REGULAR PAPERS, VOL. 53, NO. 9, SEPTEMBER 2006 An Efficient Pre-Traceback Architecture for the
 

Summary: 1918 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--I: REGULAR PAPERS, VOL. 53, NO. 9, SEPTEMBER 2006
An Efficient Pre-Traceback Architecture for the
Viterbi Decoder Targeting Wireless
Communication Applications
Yao Gang, Ahmet T. Erdogan, and Tughrul Arslan, Member, IEEE
Abstract--A large portion of silicon area and the energy con-
sumed by the Viterbi decoder (VD) is dedicated to the survivor
memory and the access operations associated with it. In this
work, an efficient pre-traceback architecture for the survivor-path
memory unit (SMU) of high constraint length VD targeting wire-
less communication applications is proposed. Compared to the
conventional traceback approach which is based on three kinds
of memory access operations: decision bits write, traceback read,
and decode read, the proposed architecture exploits the inherent
parallelism between the decision bit write and decode traceback op-
eration by introducing pre-traceback operation. Consequently, the
proposed pre-traceback approach reduces the survivor memory
read operations by 50%. As a result of the reduction of the memory
access operations, compared to the conventional 2-pointer trace-
back algorithm, the size of the survivor memory as well as the

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering