Summary: Exploiting Choice: Instruction Fetch and Issue on an Implementable
Simultaneous Multithreading Processor
Dean M. Tullsen \Lambda , Susan J. Eggers \Lambda , Joel S. Emer y , Henry M. Levy \Lambda ,
Jack L. Lo \Lambda , and Rebecca L. Stamm y
\Lambda Dept of Computer Science and Engineering y Digital Equipment Corporation
University of Washington HLO2­3/J3
Box 352350 77 Reed Road
Seattle, WA 98195­2350 Hudson, MA 01749
Abstract
Simultaneous multithreading is a technique that permits multiple
independent threads to issue multiple instructions each cycle. In
previous work we demonstrated the performance potential of si­
multaneous multithreading, based on a somewhat idealized model.
In this paper we show that the throughput gains from simultaneous
multithreading can be achieved without extensive changes to a con­
ventional wide­issue superscalar, either in hardware structures or
sizes. We present an architecture for simultaneous multithreading
that achieves three goals: (1) it minimizes the architectural impact
on the conventional superscalar design, (2) it has minimal perfor­
mance impact on a single thread executing alone, and (3) it achieves

Source: Anderson, Richard - Department of Computer Science and Engineering, University of Washington at Seattle
Wang, Deli - Department of Electrical and Computer Engineering, University of California at San Diego

Collections: Computer Technologies and Information Sciences; Engineering; Materials Science