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THE INHERENT QUEUING DELAY OF PARALLEL PACKET SWITCHES
 

Summary: THE INHERENT QUEUING DELAY OF
PARALLEL PACKET SWITCHES
(Extended Abstract)
Hagit Attiya
and David Hay
Department of Computer Science
Technion -- Israel Institute of Technology
Haifa 32000, Israel
{hagit,hdavid}@cs.technion.ac.il
Abstract The parallel packet switch (PPS) is extensively used as the core of con-
temporary commercial switches. This paper investigates the inherent
queuing delay and delay jitter introduced by the PPS's demultiplexing
algorithm, relative to an optimal work-conserving switch.
We show that the inherent queuing delay and delay jitter of a sym-
metric and fault-tolerant N ŚN PPS, where every demultiplexing algo-
rithm dispatches cells to all the middle-stage switches is (N), if there
are no buffers in the PPS input-ports. If the demultiplexing algorithms
dispatch cells only to part of the middle-stage switches, the queuing
delay and delay jitter are (N/S), where S is the PPS speedup. These
lower bounds hold unless the demultiplexing algorithm has full and im-

  

Source: Attiya, Hagit - Department of Computer Science, Technion, Israel Institute of Technology

 

Collections: Computer Technologies and Information Sciences