Home

About

Advanced Search

Browse by Discipline

Scientific Societies

E-print Alerts

Add E-prints

E-print Network
FAQHELPSITE MAPCONTACT US


  Advanced Search  

 
Distrib. Comput. (1999) 12: 5759 c Springer-Verlag 1999
 

Summary: Distrib. Comput. (1999) 12: 57­59
c Springer-Verlag 1999
Sequential consistency and the lazy caching algorithm
Rob Gerth
Intel Microprocessor Products Group, Strategic CAD Laboratories (SCL), 5200 NE Elam Young Parkway, JFT-104, Hillsboro, OR 97124-6497, USA
(e-mail: robgerth@ichips.intel.com)
Summary. I introduce and discuss sequential consistency,
a relaxed memory model, and define what it means for a
protocol to implement sequential consistency. Then, I intro-
duce the lazy caching protocol of Afek, Brown and Mer-
rit [ABM93] and formalize it as a labeled transition system.
Key words: Sequential consistency ­ Weak memory models
­ Cache coherency ­ Parallel program verification
1 Introduction
In large multiprocessor architectures the design of efficient
shared memory systems is important because the latency im-
posed on the processors when reading or writing should be
kept at a minimum. This is usually achieved by interpos-
ing a cache memory between each processor and the shared
memory system. A cache is private to a processor and con-

  

Source: Ábrahám, Erika - Fachgruppe Informatik, Rheinisch Westfälische Technische Hochschule Aachen (RWTH)

 

Collections: Computer Technologies and Information Sciences