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Optimal design of synchronous circuits using software pipelining techniques

Summary: Optimal design of synchronous circuits using
software pipelining techniques
Fran¸cois R. Boyer
El Mostapha Aboulhamid
Universit´e de Montr´eal
Yvon Savaria
´Ecole Polytechnique de Montr´eal
Michel Boyer
Universit´e de Montr´eal
We present a method to optimize clocked circuits by relocating and changing the time of activation
of registers to maximize the throughput. Our method is based on a modulo scheduling algorithm
for software pipelining, instead of retiming. It optimizes the circuit without the constraint on
the clock phases that retiming has, which permits to always achieve the optimal clock period.
The two methods have the same overall time complexity, but we avoid the computation of all
pair-shortest paths, which is a heavy burden regarding both space and time. From the optimal
schedule found, registers are placed in the circuit without looking at where the original registers
were. The resulting circuit is a multi-phase clocked circuit, where all the clocks have the same


Source: Aboulhamid, El Mostapha - Département d'Informatique et recherche opérationnelle, Université de Montréal
Boyer, Francois. R . - Département de Génie Informatique, École Polytechnique de Montréal


Collections: Computer Technologies and Information Sciences; Engineering