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T. Srikanthan et al. (Eds.): ACSAC 2005, LNCS 3740, pp. 15 27, 2005. Springer-Verlag Berlin Heidelberg 2005
 

Summary: T. Srikanthan et al. (Eds.): ACSAC 2005, LNCS 3740, pp. 15 ­27, 2005.
© Springer-Verlag Berlin Heidelberg 2005
Energy-Effective Instruction Fetch Unit for
Wide Issue Processors
Juan L. Aragón1
and Alexander V. Veidenbaum2
1
Dept. Ingen. y Tecnología de Computadores,
Universidad de Murcia, 30071 Murcia, Spain
jlaragon@ditec.um.es
2
Dept. of Computer Science,
University of California, Irvine, 92697-3425 Irvine, CA, USA
alexv@cecs.uci.edu
Abstract. Continuing advances in semiconductor technology and demand for
higher performance will lead to more powerful, superpipelined and wider issue
processors. Instruction caches in such processors will consume a significant
fraction of the on-chip energy due to very wide fetch on each cycle. This paper
proposes a new energy-effective design of the fetch unit that exploits the fact
that not all instructions in a given I-cache fetch line are used due to taken

  

Source: Aragón Alcaraz, Juan Luis - Departamento de Ingenieria y Tecnologia de Computadores, Universidad de Murcia

 

Collections: Computer Technologies and Information Sciences