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Summary: ABSTRACT
We introduce a new verification methodology for modern micro-
processors that uses a simple checker processor to validate the exe-
cution of a companion high-performance processor. The checker
can be viewed as an at-speed emulator that is formally verified to be
compliant to an ISA specification. This verification approach en-
ables the practical deployment of formal methods without impact-
ing overall performance.
1. INTRODUCTION
Modern microprocessors are enormously complex systems. Archi-
tectural features, such as out-of-order and speculative execution,
branch prediction, and multi-level caches, significantly enhance
performance but create serious functional verification challenges.
By far, the most common verification paradigm in use today is sim-
ulation. A typical microprocessor design is simulated for months us-
ing a battery of test programs that are intended to "wring the bugs
out" before the design is released for manufacture. Such a verifica-
tion strategy is becoming increasingly untenable, however, because
of increasing design complexity and time-to-market pressures. In
addition, simulation-based verification cannot guarantee that a de-
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