Home

About

Advanced Search

Browse by Discipline

Scientific Societies

E-print Alerts

Add E-prints

E-print Network
FAQHELPSITE MAPCONTACT US


  Advanced Search  

 
LOW POWER DCT IMPLEMENTATION APPROACH FOR VLSI DSP PROCESSORS S. Masupe and T. Arslan
 

Summary: LOW POWER DCT IMPLEMENTATION APPROACH FOR VLSI DSP PROCESSORS
S. Masupe and T. Arslan
The University of Edinburgh
Department of Electronics and Electrical Engineering
Mayfield Rd., Edinburgh EH9 3JL, United Kingdom
ABSTRACT
This paper presents an algorithm for the low power
implementation of the Discrete Cosine Transform on
Single multiplier CMOS DSPs. The algorithm reduces
power by a combination of using shift operations, where
possible, and manipulatingbit-correlation between suc-
cessive cosine coefficients applied to the input of the
multiplier section such that the effective switched ca-
pacitance is reduced. This reduces the switching activ-
ity in the multiplication of a Discrete Cosine Trans-
form processor. The paper describes the algotrithm,
the evaluation procedure and presents results with a
number of example images illustratingupto 50 power
savings.
1. INTRODUCTION

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering