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Cache-Aware Real-Time Scheduling on Multicore Platforms: Heuristics and a Case Study
 

Summary: Cache-Aware Real-Time Scheduling on Multicore Platforms:
Heuristics and a Case Study
John M. Calandrino and James H. Anderson
Department of Computer Science, The University of North Carolina at Chapel Hill
Abstract
Multicore architectures, which have multiple processing
units on a single chip, have been adopted by most chip man-
ufacturers. Most such chips contain on-chip caches that are
shared by some or all of the cores on the chip. To effec-
tively use the available processing resources on such plat-
forms, scheduling methods must be aware of these caches. In
this paper, we explore various heuristics that attempt to im-
prove cache performance when scheduling real-time work-
loads. Such heuristics are applicable when multiple multi-
threaded applications exist with large working sets. In ad-
dition, we present a case study that shows how our best-
performing heuristics can improve the end-user performance
of video encoding applications.
1 Introduction
Multicore architectures, which contain multiple processing

  

Source: Anderson, James - Department of Computer Science, University of North Carolina at Chapel Hill

 

Collections: Computer Technologies and Information Sciences