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Summary: WearMon: Reliability Monitoring Using Adaptive Critical Path Testing
Bardia Zandian*, Waleed Dweik, Suk Hun Kang, Thomas Punihaole, Murali Annavaram
Electrical Engineering Department, University of Southern California
{bzandian,dweik,sukhunka,punihaol,annavara}@usc.edu
Abstract
As processor reliability becomes a first order design con-
straint, this research argues for a need to provide continu-
ous reliability monitoring. We present WearMon, an adap-
tive critical path monitoring architecture which provides
accurate and real-time measure of the processor's timing
margin degradation. Special test patterns check a set of
critical paths in the circuit-under-test. By activating the
actual devices and signal paths used in normal operation
of the chip, each test will capture up-to-date timing mar-
gin of these paths. The monitoring architecture dynamically
adapts testing interval and complexity based on analysis of
prior test results, which increases efficiency and accuracy
of monitoring. Experimental results based on FPGA im-
plementation show that the proposed monitoring unit can
be easily integrated into existing designs. Monitoring over-
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