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Abstract--Two decoding schedules and the corresponding serialized architectures for low-density parity-check (LDPC)
 

Summary: Abstract--Two decoding schedules and the corresponding
serialized architectures for low-density parity-check (LDPC)
decoders are presented. They are applied to codes with parity-
check matrices generated either randomly or using geometric
properties of elements in Galois fields. Both decoding
schedules have low computational requirements. The original
concurrent decoding schedule has a large storage requirement
that is dependent on the total number of edges in the
underlying bipartite graph, while a new, staggered decoding
schedule which uses an approximation of the belief
propagation, has a reduced memory requirement that is
dependent only on the number of bits in the block. The
performance of these decoding schedules is evaluated through
simulations on a magnetic recording channel.
I. INTRODUCTION
Sequences of Low Density Parity Check (LDPC) codes have
been demonstrated to achieve information rates very close to the
Shannon limit when iteratively decoded [1]. Using the message-
passing algorithm, LDPC decoders require an order of magnitude
less arithmetic computations than equivalent Turbo decoders [2].

  

Source: Anantharam, Venkat - Department of Electrical Engineering and Computer Sciences, University of California at Berkeley
California at Berkeley, University of - Department of Electrical Engineering and Computer Sciences, Berkeley Wireless Research Center
Nikolic, Borivoje - Department of Electrical Engineering and Computer Sciences, University of California at Berkeley

 

Collections: Engineering