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Minimum Register Instruction Sequencing to Reduce Register Spills in OutofOrder Issue Superscalar Architectures
 

Summary: Minimum Register Instruction Sequencing to Reduce Register
Spills in Out­of­Order Issue Superscalar Architectures
R. Govindarajan, Hongbo Yang, Jos’ e Nelson Amaral, Chihong Zhang, Guang R. Gao 
Abstract
In this paper we address the problem of generating an optimal instruction sequence S for a
Directed Acyclic Graph (DAG), where S is optimal when it uses a minimum number of registers.
We call this the Minimum Register Instruction Sequence (MRIS) problem. The motivation for
studying the MRIS problem stems from several modern architecture innovations/requirements that
put the instruction sequencing problem in a new context.
We develop an efficient heuristic solution for the MRIS problem. This solution is based on
the notion of an instruction lineage --- a set of instructions that can definitely share a single reg­
ister. The formation of lineages exploits the structure of the dependence graph to facilitate the
sharing of registers not only among instructions within a lineage, but also across lineages. Our
efficient heuristics to ``fuse'' lineages further reduce the register requirement. This reduced register
requirement results in generating code sequence with fewer register spills.
We implemented our solution in the MIPSpro production compiler and measured the perfor­
mance on the SPEC95 floating point benchmark suite. Our experimental results demonstrate that
the proposed instruction sequencing method significantly reduces the number of spill loads and
stores inserted in the code, by more than 50% in each of the benchmarks. Our approach reduces
the average number of dynamic loads and stores executed by 10.4% and 3.7%, respectively. Fur­

  

Source: Amaral, José Nelson - Department of Computing Science, University of Alberta

 

Collections: Computer Technologies and Information Sciences