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Power Tradeo#s in Asynchronous Interfaces D. K. Arvind # and Kristian Hildingsson
 

Summary: Power Tradeo#s in Asynchronous Interfaces
D. K. Arvind # and Kristian Hildingsson
Institute for Computing Systems Architecture
Division of Informatics, The University of Edinburgh
Edinburgh EH9 3JZ, Scotland
Abstract
This paper investigates the influence on the power consumption of partitioning a system­on­a­chip into
locally­clocked modules called Temporal Regions, and replacing its global clock with a four­phased asyn­
chronous protocol. Energy dissipation measurements are presented for an implementation of a JPEG encoder
chip implemented in 0.35µm CMOS process in a design environment based on commercial EDA tools.
1 Introduction
This paper explores the e#cacy of partitioning a system­on­a­chip into Temporal Regions (TR), where the timing
within each TR is governed by locally­generated clocks, and the operations between the TRs are controlled by
four­phase asynchronous protocols. The removal of the global clock o#ers some potential advantages: a prominent
source of energy consumption is now eliminated; the clocking in each TR can be optimised by distributing the
clock over a smaller area and its frequency can be tailored to local requirements in each TR. We first examine
the design of one such asynchronous interface, and measure the energy dissipation in the interface and the clock
net for di#erent­sized TRs. These results were derived for a JPEG encoder chip (approximately 100,000 gates)
implemented in a 0.35µm CMOS process in a design environment based on commercial EDA tools, such as Design
Compiler (synthesis) and PowerMill (power measurement) from Synopsys and Silicon Ensemble (place and route)

  

Source: Arvind, D. K. - School of Informatics, University of Edinburgh

 

Collections: Computer Technologies and Information Sciences