Home

About

Advanced Search

Browse by Discipline

Scientific Societies

E-print Alerts

Add E-prints

E-print Network
FAQHELPSITE MAPCONTACT US


  Advanced Search  

 
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 6, NO. 3, SEPTEMBER 1998 507 Testability Analysis and Behavioral Testing of the Hopfield Neural Paradigm
 

Summary: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 6, NO. 3, SEPTEMBER 1998 507
Testability Analysis and Behavioral Testing of the Hopfield Neural Paradigm
C. Alippi, Franco Fummi, V. Piuri, M. Sami, and Donatella Sciuto
Abstract--Testability analysis and test pattern generation for
neural architectures can be performed at a very high abstraction
level on the computational paradigm. In this paper, we consider
the case of Hopfield's networks, as the simplest example of
networks with feedback loops. A behavioral error model based
on finite-state machines (FSM's) is introduced. Conditions for
controllability, observability and global testability are derived to
verify errors excitation and propagation to outputs. The proposed
behavioral test pattern generator creates the minimum length test
sequence for any digital implementation.
Index Terms--FSM, functional TPG, neural network.
I. INTRODUCTION
INCREASING complexity of VLSI systems has accelerated
a trend to take into account testability and test generation
throughout the synthesis process, since the highest abstraction
levels [5]. This involves defining testability parameters, error
models and test patterns based on technology-independent,

  

Source: Alippi, Cesare - Dipartimento di Elettronica e Informazione, Politecnico di Milano

 

Collections: Computer Technologies and Information Sciences