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Statistical timing and leakage power analysis of PD-SOI digital Kyung Ki Kim Yong-Bin Kim
 

Summary: Statistical timing and leakage power analysis of PD-SOI digital
circuits
Kyung Ki Kim Yong-Bin Kim
Received: 15 December 2007 / Revised: 28 August 2008 / Accepted: 28 August 2008 / Published online: 3 October 2008
Springer Science+Business Media, LLC 2008
Abstract This paper presents a fast statistical static tim-
ing and leakage power analysis in Partially-Depleted
Silicon-On-Insulator (PD-SOI) CMOS circuits in BSIM-
SOI3.2 100 nm technology. The proposed timing analysis
considers floating body effect on the propagation delay for
more accurate timing analysis in PD-SOI CMOS circuits.
The accuracy of modeling the leakage power in PD-SOI
CMOS circuits is improved by considering the interactions
between the subthreshold leakage and the gate tunneling
leakage, the stacking effect, the history effect, and the
fanout effect. The proposed timing and leakage power
analysis algorithms are implemented in Matlab, Hspice,
and C language. The proposed methodology is applied to
ISCAS85 benchmarks, and the results show that the error is
within 5% compared with random simulation results.

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering