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Exploiting Powerup Delay for Sequential Optimization Vigyan Singhal \Lambda Carl Pixley y Adnan Aziz z Robert K. Brayton z
 

Summary: Exploiting Power­up Delay for Sequential Optimization
Vigyan Singhal \Lambda Carl Pixley y Adnan Aziz z Robert K. Brayton z
Abstract
Recent work has identified the notion of safe replacement for se­
quential synchronous designs that may not have reset hardware or
even explicitly known initial states. Safe replacement requires that
a replacement design be indistinguishable from the original from
the very first clock cycle after power­up. However, in almost any
realistic application, the design is allowed to stabilize for many
clock cycles before it is used. In this paper, we investigate the
safety of a replacement if the replacement design is allowed to be
clocked some cycles (that is, delayed) with arbitrary inputs before
the design is reset. Having argued the safety of ``delay'' replace­
ments, we investigate a new method of sequential optimization
based upon the notion. We present experimental results to demon­
strate that significant area optimizations can be gained by using
this new notion of delay replaceability, and that there is a trade­off
between the allowed number of clock cycles after power­up and
the amount of optimization that can be obtained.
1 Introduction

  

Source: Aziz, Adnan - Department of Electrical and Computer Engineering, University of Texas at Austin

 

Collections: Computer Technologies and Information Sciences