Advanced Search

Browse by Discipline

Scientific Societies

E-print Alerts

Add E-prints

E-print Network

  Advanced Search  

Low power multi-segment sequential one hot addressing architecture

Summary: Low power multi-segment sequential one hot
addressing architecture
K.-C.B. Tan and T. Arslan
Abstract: Sequential addressing is one of the essential power-consuming parts of digital signal
processing (DSP), which is mainly used for sequential memory and coefficient selection. The use of
sequential addressing is not only widespread, but also particularly important in a wide variety of
DSP applications as most of the computation process proceeds in a sequential manner. Therefore,
by reducing both the power of the sequential memory addressing hardware and accesses within the
DSP system, the overall power consumption of the system will be effectively reduced. A novel
scalable low power multi-segment one-hot all-sequential addressing architecture (MSML-OHA) is
presented. This architecture, implemented in 0.18mm CMOS technology, reduces power dissipation
by more than 20% compared to conventional counter-decoder architecture.
1 Introduction
High-speed, low-level, essential and repetitive sequential
tasks in high throughput DSP systems are often the parts of
the system that consume a considerable amount of power.
One such essential power-consuming component of a DSP
system is the address decoder or local addressing logic,
which is used mainly for sequential memory selection. So
far, no one has targeted their research into reducing internal


Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh


Collections: Engineering