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Figure 1. 9T SRAM cell in [3] A Highly-Stable Nanometer Memory for Low-Power Design
 

Summary: Figure 1. 9T SRAM cell in [3]
A Highly-Stable Nanometer Memory for Low-Power Design
Sheng Lin, Yong-Bin Kim, and Fabrizio Lombardi
Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA
{slin; ybk; lombardi}@ece.neu.edu
Abstract
A nine transistor (9T) cell at a 32nm feature size in
CMOS is proposed to accomplish improvements in
stability as well as power dissipation compared with
previous designs for low-power memory operation.
Initially, this paper shows that the proposed 9T SRAM
cell can be used for robust, high-density design. Then,
an optimum sizing is found for this 9T cell by
considering stability, energy consumption, and
performance. A write bitline balancing scheme is
proposed to further reduce the power consumption of
the SRAM cell. The impact of process variations is
investigated in detail, and the power reduction of the
9T SRAM cell is verified under parameter variations.
1. Introduction

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering