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Performance Driven Synthesis for PassTransistor Logic \Lambda TaiHung Liu Adnan Aziz Jeffrey L. Burns
 

Summary: Performance Driven Synthesis for Pass­Transistor Logic \Lambda
Tai­Hung Liu Adnan Aziz Jeffrey L. Burns
Department of Electrical and Computer Engineering Austin Research Laboratory
The University of Texas at Austin IBM Corporation
Austin, TX 78712 Austin, TX 78758
Abstract
For many digital designs, implementation in pass­transistor logic
(PTL) has been shown to be superior in terms of area, timing,
and power characteristics to static CMOS. Binary Decision Dia­
grams (BDDs) have been used for PTL synthesis because of the
close relationship between BDDs and PTL. Thus far, BDD opti­
mization for PTL synthesis has targeted minimizing the number of
BDD nodes. This strategy leads to smaller PTL implementations,
but it can result in extremely slow circuits. In this paper, we model
the delay of PTL circuits derived from BDDs, and propose pro­
cedures to reduce the worst­case delay or the area­delay product
of such circuits. The experimental results show a significant im­
provement in the delay (36%) and area­delay product (17%) for the
ISCAS benchmark circuits.
1 Introduction

  

Source: Aziz, Adnan - Department of Electrical and Computer Engineering, University of Texas at Austin

 

Collections: Computer Technologies and Information Sciences