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Accelerating Trace Computation in Post-Silicon Debug Johnny J.W. Kuan, Steven J.E. Wilton, Tor M. Aamodt
 

Summary: Accelerating Trace Computation in Post-Silicon Debug
Johnny J.W. Kuan, Steven J.E. Wilton, Tor M. Aamodt
Department of Electrical and Computer Engineering
University of British Columbia, Vancouver, BC, Canada
Email: {jkuan, stevew, aamodt}@ece.ubc.ca
Abstract-- Post-silicon debug comprises a significant
and highly variable fraction of the total development time
for large chip designs. To accelerate post-silicon debug,
BackSpace [1, 2] employs on-chip monitoring circuitry and
off-chip formal analysis to provide a trace of states that lead
up to a crash state. BackSpace employs repeated runs of
the integrated circuit being debugged, which can be time
consuming. This paper shows that correlation information
characterizing the application running on the hardware up to
the crash state can reduce the number of runs of the chip by
up to 51%.
1. Introduction
Post-silicon debug (also known as silicon validation) is the
process of determining what is wrong when the fabricated
chip of a new design behaves incorrectly. The focus of post-

  

Source: Aamodt, Tor - Department of Electrical and Computer Engineering, University of British Columbia

 

Collections: Engineering; Computer Technologies and Information Sciences