Summary: Reconciling Performance and Programmability in
Networking Systems
Jayaram Mudigonda

Harrick M. Vin Stephen W. Keckler
Department of Computer Sciences, The University of Texas, Austin TX 78712 USA.
{jram|vin|skeckler}@cs.utexas.edu
ABSTRACT
Challenges in addressing the memory bottleneck have made
it difficult to design a packet processing platform that si-
multaneously achieves both ease-of-programming and high
performance. Today's commercial processors support two
architectural mechanisms­namely, hardware multithreading
and caching­to overcome the memory bottleneck. The con-
figurations of these mechanisms (e.g., cache capacity, num-
ber of threads per processor core) are fixed at processor-
design time. The relative effectiveness of these mechanisms,
however, varies significantly with application, traffic, and
system characteristics. Thus, programmers often struggle
to achieve high performance from a processor that is not

Source: Akella, Aditya - Department of Computer Sciences, University of Wisconsin at Madison
Keckler, Stephen W. - Department of Computer Sciences, University of Texas at Austin

Collections: Computer Technologies and Information Sciences