Advanced Search

Browse by Discipline

Scientific Societies

E-print Alerts

Add E-prints

E-print Network

  Advanced Search  

A Speculative Control Scheme for an Energy-Efficient Banked Register File

Summary: A Speculative Control Scheme for an
Energy-Efficient Banked Register File
Jessica H. Tseng, Student Member, IEEE, and Krste Asanovicc, Member, IEEE
Abstract--Multiported register files are critical components of modern superscalar and simultaneously multithreaded (SMT)
processors, but conventional designs consume considerable die area and power as register counts and issue widths grow. Banked
multiported register files consisting of multiple interleaved banks of lesser ported cells can be used to reduce area, power, and access
time and previous work has shown that such designs can provide sufficient bandwidth for a superscalar machine. These previous
banked designs, however, have complex control structures to avoid bank conflicts or to buffer conflicting requests, which add to design
complexity and would likely limit cycle time. This paper presents a much simpler and faster control scheme that speculatively issues
potentially conflicting instructions, then quickly repairs the pipeline if conflicts occur. We show that, once optimizations to avoid regfile
reads are employed, the remaining read accesses observed in detailed simulations are close to randomly distributed and this
contributes to the effectiveness of our speculative control scheme. For a four-issue superscalar processor with 64 physical registers,
we show that we can reduce area by a factor of three, access time by 25 percent, and energy by 40 percent, while decreasing IPC by
less than 5 percent. For an eight-issue SMT processor with 512 physical registers, area is reduced by a factor of seven, access time by
30 percent, and energy by 60 percent, while decreasing IPC by less than 2 percent.
Index Terms--Low-power, register file, speculative control, superscalar, simultaneous multithreading.

MULTIPORTED register files and bypass networks lie at the
heart of a superscalar microprocessor and provide


Source: Asanovic, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)


Collections: Computer Technologies and Information Sciences