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Summary: COURSE SUMMARY
· Verification of Digital Systems
Systematic approaches to checking the functional correct-
ness of synchronous digital systems
· Design Representation
Netlists
Syntax
Various Semantics
Compositionality
Intuitively, trying to model cycle-accurate designs (not nec-
essarily Boolean)
+ Simple model, quite powerful
- Cycle accuracy precludes abstraction
· FSMs
strictly higher level of abstraction than netlists
formally in terms of tuples, intuitively graphs
· Design Equivalence
Key: equivalence with respect to input-output behavior
DIS assumption
Notion of safe replaceability
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