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On the Generation of Test Patterns for Multiple Faults
Younès KARKOURI, El Mostapha ABOULHAMID and Eduard CERNY
Dép. d'informatique et de recherche opérationnelle
Université de Montréal, C.P. 6128, Succ. "A"
Montréal, (Québec), H3C-3J7, Canada.
This paper presents a new method to generate test patterns for multiple stuck-at faults in combinational
circuits. We assume the presence of all multiple faults of all multiplicities and we do not resort to their explicit
enumeration: the target fault is a single component of possibly several multiple faults. New line and gate
models are introduced to handle multiple fault effect propagation through the circuits. The method tries to
generate test conditions that propagate the effect of the target fault to primary outputs. When these conditions
are fulfilled, the input vector is a test for the target fault and it is guaranteed that all multiple faults of all
multiplicities containing the target fault as component are also detected. The method uses similar techniques to
those in the FAN and SOCRATES algorithms to guide the search part of the algorithm and includes several
new heuristics to enhance the performance and fault detection capability. Experiments performed on the
ISCAS'85 benchmark circuits show that test sets for multiple faults can be generated with high fault coverage
and a reasonable increase in cost over test generation for single stuck-at faults.
Keywords: combinational circuits, stuck-at faults, multiple faults, fault analysis, test pattern generation.
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