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AXCIS: Rapid Processor Architectural Exploration using Canonical Instruction Segments
 

Summary: AXCIS: Rapid Processor Architectural Exploration using
Canonical Instruction Segments
by
Rose F. Liu
S.B., Massachusetts Institute of Technology (2004)
Submitted to the Department of Electrical Engineering and Computer
Science
in partial fulfillment of the requirements for the degree of
Master of Engineering in Electrical Engineering and Computer Science
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
September 2005
c

Massachusetts Institute of Technology 2005. All rights reserved.
Author . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Department of Electrical Engineering and Computer Science
August 16, 2005
Certified by . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Krste Asanovi┤c

  

Source: AsanoviŠ, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)
Massachusetts Institute of Technology (MIT), Computer Science and Artificial Intelligence Laboratory, SCALE Group

 

Collections: Computer Technologies and Information Sciences