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Summary: 18
Paging: Faster Translations (TLBs)
When we want to make things fast, the OS needs some help.
And help usually comes from one place: the hardware. To speed
address translation, we are going to add what is called (for his-
torical reasons [CP78]) a translation-lookaside buffer, or TLB
[C68,C95]. A TLB is part of the chip's memory-management
unit (MMU), and is simply a hardware cache of popular virtual-
to-physical address translations; thus, a better name would be
an address-translation cache. Upon each virtual memory ref-
erence, the hardware first checks the TLB to see if the desired
translation is held therein; if so, the translation is performed
(quickly) without having to consult the page table (which has all
translations). Because of their tremendous performance impact,
TLBs in a real sense make virtual memory possible [C95].
Figure 18.1 shows how hardware might handle a virtual ad-
dress translation (assuming a simple linear page table and a
hardware-managed TLB). In the common case (lines 39), we
are hoping that a translation will be found in the TLB (a TLB
hit) and thus the translation will be quite fast (done in hard-
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