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Summary: Dynamic Capacity-Speed Tradeoffs
in SMT Processor Caches
Sonia L´opez1
, Steve Dropsho2
, David H. Albonesi3
,
Oscar Garnica1
, and Juan Lanchares1
1
Departamento de Arquitectura de Computadores y Automatica,
U. Complutense de Madrid, Spain
2
School of Computer and Communication Science, EPFL, Switzerland
3
Computer Systems Laboratory, Cornell University, USA
Abstract
Caches are designed to provide the best tradeoff between access speed and capacity
for a set of target applications. Unfortunately, different applications, and even different
phases within the same application, may require a different capacity-speed tradeoff.
This problem is exacerbated in a Simultaneous Multi-Threaded (SMT) processor where
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