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Low power system on chip bus encoding scheme with crosstalk noise reduction capability
 

Summary: Low power system on chip bus encoding scheme
with crosstalk noise reduction capability
Z. Khan, T. Arslan and A.T. Erdogan
Abstract: Inter-wire coupling is a major source of wire load and delay faults for on-chip buses
implemented in ultra-deep submicron system on chip (SoC) systems. Elimination or minimisation
of such faults is crucial to the performance and reliability of SoC designs. A novel on-chip bus
encoding scheme targeting high-performance generic SoC systems is presented. In addition to
its efficiency in terms of power, the scheme reduces delay faults by completely eliminating the
most critical type of crosstalk coupled switched capacitance. The authors describe the technique
and its implementation (using the widely adopted AMBA-AHB SoC bus standard) and provide
experimental results indicating 2236% energy saving for systems implemented in 0.18 mm
CMOS technology.
1 Introduction
The scaling of complementary metal-oxide-semiconductor
(CMOS) technology to ultra-deep submicron has increased
the sensitivity of CMOS technology to various noise
mechanisms such as crosstalk noise, power supply noise,
leakage noise and so on. Of all these, the crosstalk noise
because of capacitive coupling is dominant, as it causes
delay faults, logical malfunctions and energy consumption

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering