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A Low Power 32 Nanometer CMOS Digitally Controlled Oscillator Jun Zhao, Yong-bin Kim
 

Summary: A Low Power 32 Nanometer CMOS Digitally Controlled Oscillator
Jun Zhao, Yong-bin Kim
Northeastern University
Boston, MA, USA
(jzhao@ece.neu.edu, ybk@ece.neu.edu)
ABSTRACT
In this paper, a low power and low jitter 12-bit
CMOS digitally controlled oscillator (DCO) design is
presented. The CMOS DCO design is based on a
ring oscillator implemented with Schmitt trigger
based inverters. Simulations of the proposed DCO
using 32nm Predictive Transistor Model (PTM)
achieve controllable frequency range of around
570MHz~850MHz with a wide range of linearity.
Monte Carlo simulation demonstrates that the time-
period jitter due to random power supply fluctuation
is under 75ps and the power consumption is
2.3mW at 800MHz and 0.9 power supply.
I. INTRODUCTION
Over the past two decades, the operating clock

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering