Summary: In Proceedings of ASPLOS­VII (October, 1996)
An Evaluation of Memory Consistency Models
for Shared­Memory Systems with ILP Processors
Vijay S. Pai, Parthasarathy Ranganathan, Sarita V. Adve, and Tracy Harton
Department of Electrical and Computer Engineering
Rice University
Houston, Texas 77251­1892
fvijaypaijparthasjsaritajhartong@rice.edu
Abstract
Relaxed consistency models have been shown to significantly
outperform sequential consistency for single­issue, statically
scheduled processors with blocking reads. However, current
microprocessors aggressively exploit instruction­level paral­
lelism (ILP) using methods such as multiple issue, dy­
namic scheduling, and non­blocking reads. Researchers have
conjectured that two techniques, hardware­controlled non­
binding prefetching and speculative loads, have the potential
to equalize the hardware performance of memory consistency
models on such processors.
This paper performs the first detailed quantitative com­

Source: Adve, Sarita - Department of Computer Science, University of Illinois at Urbana-Champaign

Collections: Computer Technologies and Information Sciences