 
Summary: Logic Optimization of Designs Containing Black Boxes
Abstract
We define a notion of equivalence for designs containing black boxes. Using this notion, we
describe a sound and complete methodology for optimizing designs containing black boxes, i.e.
components whose functionality is not known; these arise naturally in the course of hierarchical
design.
Keywords: Hierarchical Logic Synthesis, Black Boxes, Don't Cares
1 Introduction
The advent of modern VLSI CAD tools has radically changed the process of designing digital systems.
The first CAD tools automated the final stages of design, such as placement and routing. As the low
level steps became better understood, the focus shifted to the higher stages. In particular logic synthesis,
the science of optimizing gate level designs for measures such as area, speed, or power, has shifted to
the forefront of CAD research.
Logic synthesis algorithms originally targeted the optimization of PLA implementations [4]; this
was followed by research in synthesizing more general multilevel logic implementations. Currently, the
central thrust in logic synthesis is sequential synthesis, i.e. the automatic optimization of the entire
system. This is for designs specified at the structural level in the form of netlists, or at the behavioral
level, i.e. in the form of finite state machines. DeMicheli [15] gives an excellent introduction to logic
synthesis.
Typically, the synthesis process has two stages: first, the set of all possible implementations is
