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Distributed Reconfiguration of Fault Tolerant VLSI Multipipeline Arrays with Constant Interstage Path Lengths
 

Summary: Distributed Reconfiguration of Fault Tolerant VLSI
Multipipeline Arrays with Constant Interstage Path Lengths
Hussain Al-Asaad, Mankuan Vai , and James Feldman
Department of Electrical and Computer Engineering
Northeastern University
Boston, MA 02115
Abstract
A new fault tolerant multipipeline array
architecture and its diagnosis/reconfiguration
algorithm will be presented. This multipipeline
array design methodology is characterized by
constant, fault distribution independent interstage
path lengths. Other features include a low hardware
overhead and a high survival rate when it is
compared to existing approaches.
1: Introduction
The pipeline stages of a multipipeline array are
separated from each other by interconnection
networks as shown in Fig. 1. Interconnection
networks ranging from simple feed-through

  

Source: Al-Asaad, Hussain - Department of Electrical and Computer Engineering, University of California, Davis

 

Collections: Computer Technologies and Information Sciences