Summary: A Low Energy VLSI Design of Random Block Interleaver for 3GPP Turbo
Imran Ahmed, Tughrul Arslan
School of Electronics and Engineering. Institute for System Level Integration, The Alba
University of Edinburgh, King's Buildings Campus, The Alba Centre, Livingston,
Mayfield Road, Edinburgh, EH9 3JL, UK Scotland, EH54 7EG, UK
Abstract code's distance spectrum, allowing practical and low
In this paper novel hardware architecture for Internal complexity decoding. The interleaver in 3GPP turbo
Random Block Interleaver compliant with the 3rd decoding is defined by a complex algorithm for generation
Generation Partnership Project (3GPP) Turbo Decoding ofinterleaved addresses.
is described. The complexity of this algorithm results in
other implementations using large Memories as address Systematicbits
tables. In this implementation real time address SaftibitsI
computation avoids the use of pre-computed address PantybisbyE coder1 D1 + Interleaver
storage. This greatly reduces the load on the processor
and gives significant improvements in area and power.
ASIC synthesis results on 0.18 Pm CMOS UMC Interleaver
technology demonstrate the efficiency of the proposed
VLSI interleaver architecture.