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Time Divergence, Timelock, and Zenoness Lecture #16 of Advanced Model Checking
 

Summary: Time Divergence, Timelock, and Zenoness
Lecture #16 of Advanced Model Checking
Joost-Pieter Katoen
Lehrstuhl 2: Software Modeling & Verification
E-mail: katoen@cs.rwth-aachen.de
January 17, 2011
c JPK
Advanced model checking
Timed automata
· Timed automaton = finite-state automaton with clock variables
· Clocks take non-negative real values, i.e., in R 0
· Clocks increase implicitly, i.e., clock updates are not allowed
· All clocks increase at the same pace, i.e., with rate one
· Clocks may only be inspected and reset to zero
· Boolean conditions on clocks are used as:
­ guards of edges: when is an edge enabled?
­ invariants of locations: how long is it allowed to stay?
c JPK 1
Advanced model checking
Clock constraints

  

Source: Ábrahám, Erika - Fachgruppe Informatik, Rheinisch Westfälische Technische Hochschule Aachen (RWTH)

 

Collections: Computer Technologies and Information Sciences