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A Novel Low Power PipelinedArchitecturefor a MC-CDMA receiver M. Hasan, T. Arslan and John Thompson
 

Summary: A Novel Low Power PipelinedArchitecturefor a MC-CDMA receiver
M. Hasan, T. Arslan and John Thompson
School of Engineering and Electronics,
The University of Edinburgh, Edinburgh EH9 3JL, UK
E-mail: mh@ee.ed.uc.uk
Abstract
This paper proposes a novel low power pipelined
architecture for a Multi-carrier code division mulriple
access (MC-CDMA)receiver. The receiver is based on
64 sub-carriers. It comprises of two blocks namely the
FFT for demodulation and the combiner for
de-spreading and equalization. The 64-point FFT block
is based on low power pipelined radix-4 architecture in
which coefJicient ordering is applied to its second stage
to further bring down its power consumption. Clock
gating is extensively used in the combiner to reduce its
power consumption.
1. Introduction
MC-CDMA [1,2] is a spread spectrum technology
which combines the advantages of OFDM (Orthogonal

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering