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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 11, NOVEMBER 2006 1281 [11] J. Lillis, C. K. Cheng, and T. T. Y. Lin, "Optimal wire sizing and buffer
 

Summary: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 11, NOVEMBER 2006 1281
[11] J. Lillis, C. K. Cheng, and T. T. Y. Lin, "Optimal wire sizing and buffer
insertion for low power and a generalized delay model," in Proc. IEEE
Int. Conf. Comput.-Aided Des., 1995, pp. 138143.
[12] C. J. Alpert and A. Devgan, "Wire segmenting for improved buffer
insertion," in Proc. Des. Autom. Conf., 1997, pp. 588593.
[13] C. J. Alpert, A. Devgan, and S. T. Quay, "Buffer insertion for noise
and delay optimization," in Proc. 34th ACM/IEEE DAC, 1999, pp.
362367.
[14] C. Chu and D. F. Wong, "Closed form solution to simultaneous buffer
insertion/sizing and wire sizing," ACM Trans. Design Autom. Electron.
Syst., vol. 6, no. 3, pp. 343371, Jul. 2001.
[15] S. Dhar and M. A. Franklin, "Optimum buffer circuits for driving long
uniform lines," IEEE J. Solid-State Circuits, vol. 26, pp. 3240, Jan.
1991.
[16] Berkeley Predictive Technology Model (BPTM), (2005) [Online].
Available: www-device.eecs.berkeley.edu/~ptm/introduction.html
[17] J. A. Davis, R. Venkatesan, K. A. Bowman, and J. D. Meindl, "Gi-
gascale integration (GSI) interconnect limits and n-tier multilevel in-
terconnect architectural solutions," in Proc. Int. Workshop Syst. Level

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering