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A Double-Pulsed Set-Conditional-Reset Flip-Flop Albert Ma and Krste Asanovic
 

Summary: 1
A Double-Pulsed Set-Conditional-Reset Flip-Flop
Albert Ma and Krste Asanovi´c
MIT Laboratory for Computer Science
200 Technology Square
Cambridge, MA 02139
ama,krste@lcs.mit.edu
Abstract--A new flip-flop design using a double-pulsed static latch is
presented. The flip-flop has only a single stage of logic in the critical path
and as a result is up to three times faster than the fastest previously known
flip-flops, while consuming approximately the same energy as the lowest-
power flip-flops. The flip-flop has asymmetric timing properties which
make it a good match to skewed logic styles. A novel dual-pulse genera-
tor further reduces power requirements.
Index Terms--flip-flop, pulsed latch
I. INTRODUCTION
Flip-flops are critical timing elements in digital circuits and
have a large impact on circuit speed and power consumption.
Consequently, extensive research has been performed to de-
velop fast and low-power flip-flops [1], [2], [3], [4]. The pri-

  

Source: Asanovic, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)
Massachusetts Institute of Technology (MIT), Computer Science and Artificial Intelligence Laboratory, SCALE Group

 

Collections: Computer Technologies and Information Sciences