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Summary: Cross-layer Resilience Using Wearout Aware Design Flow
Bardia Zandian, Murali Annavaram
Electrical Engineering Department, University of Southern California
Los Angeles, CA
{bzandian,annavara}@usc.edu
Abstract--As process technology shrinks devices, circuits
experience accelerated wearout. Monitoring wearout will be
critical for improving the efficiency of error detection and
correction. The most effective wearout monitoring approach
relies on continuously checking only the most critical circuit
paths to detect timing degradation. However, circuits
optimized for power and area efficiency have a steep critical
path wall in some designs. Furthermore, wearout depends on
dynamic conditions, such as processor's operating
environment, and application-specific path utilization profile.
The dynamic nature of wearout coupled with steep critical
path walls may result in excessive number of paths that need to
be monitored. In this paper we propose a novel cross-layer
circuit design flow that uses path timing information and
runtime path utilization data to significantly enhance
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