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INSTRUCTIONLEVEL PARALLELISM IN ASYNCHRONOUS PROCESSOR ARCHITECTURES
 

Summary: INSTRUCTION­LEVEL PARALLELISM IN ASYNCHRONOUS
PROCESSOR ARCHITECTURES
D. K. ARVIND and V. E. F. REBELLO
Department of Computer Science, The University of Edinburgh
Mayfield Road, Edinburgh EH9 3JZ, Scotland, U. K.
fdka,vefrg@dcs.ed.ac.uk
ABSTRACT. The Micronet­based Asynchronous Processor (MAP) is a family of processor
architectures based on the micronet model of asynchronous control. Micronets distribute
the control amongst the functional units which enables the exploitation of fine­grained
concurrency, both between and within program instructions. This paper introduces the mi­
cronet model and evaluates the performance of micronet­based datapaths using behavioural
simulations.
KEYWORDS. Instruction­level parallelism (ILP), asynchronous processor architecture,
self­timed design.
1 INTRODUCTION
Centralised controls have been traditionally used to correctly sequence information within
processor architectures. However, the ability to sustain this design style is under pressure
from a number of directions [6]. This paper examines the effect of relaxing this strict
synchrony on the design and performance of processor architectures. The reasons are the
following. The the clock frequency of a synchronous processor is determined a priori by the

  

Source: Arvind, D. K. - School of Informatics, University of Edinburgh

 

Collections: Computer Technologies and Information Sciences