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Algorithmic Implementation of Low-Power High Performance FIR Filtering IP Cores
 

Summary: Algorithmic Implementation of Low-Power High Performance FIR
Filtering IP Cores
C.H.Wang1
, A.T.Erdogan1,2
and T.Arslan1,2
1
University of Edinburgh, School of Engineering and Electronics
Edinburgh, EH9 3JL, Scotland, United Kingdom
2
Institute of System Level Integration, The ALBA campus
Livingston, EH54 7EG, Scotland, United Kingdom
C.Wang@sms.ed.ac.uk, Ahmet.Erdogan@ee.ed.ac.uk, Tughrul.Arslan@ee.ed.ac.uk
Abstract
This paper presents two schemes for the implemen-
tation of high performance and low power FIR filtering
Intellectual Property (IP) cores. Low power is achieved
through the utilization of algorithms such as coefficient
segmentation, block processing and combined segmenta-
tion and block processing algorithms. On the other hand,
multiple data paths are utilized for achieving high per-

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering