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Chip cooling with integrated carbon nanotube microfin architectures K. Kords, G. Tth, P. Moilanen, M. Kumpumki, J. Vhkangas, and A. Uusimki
 

Summary: Chip cooling with integrated carbon nanotube microfin architectures
K. Kordás, G. Tóth, P. Moilanen, M. Kumpumäki, J. Vähäkangas, and A. Uusimäki
Microelectronics and Materials Physics Laboratories, Department of Electrical and Information Engineering,
University of Oulu, P.O. Box 4500, FIN-90014 Oulu, Finland and EMPART Research Group of
Infotech Oulu, University of Oulu, P.O. Box 4500, FIN-90014 Oulu, Finland
R. Vajtaia
and P. M. Ajayan
Department of Materials Science and Engineering, Rensselaer Polytechnic Institute, Troy, New York 12180
and Rensselaer Nanotechnology Center, Rensselaer Polytechnic Institute, Troy, New York 12180
Received 15 January 2007; accepted 9 February 2007; published online 20 March 2007
Efficient cooling of silicon chips using microfin structures made of aligned multiwalled carbon
nanotube arrays is achieved. The tiny cooling elements mounted on the back side of the chips enable
power dissipation from the heated chips on the level of modern electronics demands. The nanotube
fins are mechanically superior compared to other materials being ten times lighter, flexible, and stiff
at the same time. These properties accompanied with the relative simplicity of the fabrication makes
the nanotube structures strong candidates for future on-chip thermal management applications.
© 2007 American Institute of Physics. DOI: 10.1063/1.2714281
High power consumption and the corresponding problem
of heat dissipation are two of the most serious limitations in
high performance electronics today. Several solutions for

  

Source: Ajayan, Pulickel M. - Department of Mechanical Engineering and Materials Science, Rice University

 

Collections: Materials Science